Error(10327):VHDLerroratxd.vhd(17):can'tdeterminedefinitionofoperator""+""--found0pos
初学VHDL~
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYxdIS
PORT(sel:INstd_logic;
d0,d1:INstd_logic;
led:OUTstd_logic);
ENDENTITYxd;
ARCHITECTUREabcOFxdIS
signalnum0:std_logic_VECTOR(7DOWNTO0);
signalnum:std_logic_VECTOR(7DOWNTO0);
BEGIN
num0